This application is related to Japanese application No. HEI9(1997)-335396, filed on Dec. 5, 1997 whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device, more particularly, to a process for fabricating a semiconductor device which enables a device isolation region of the semiconductor device to be formed flat so as to have a uniform thickness.
2. Description of Related Art
A conventional process of forming a device isolation region in a semiconductor device is described below.
First, referring to FIG. 5(a), a pad oxide film 702 and an etching-stop layer 703 are formed in sequence on a P-type semiconductor substrate 701. Then, using a resist 708 as a mask, the etching-stop layer 703 and the pad oxide film 702 are removed by etching from a region to be a device isolation region.
Subsequently, as shown in FIG. 5(b), using the resist 708 as a mask, the semiconductor substrate 701 is further etched to form a trench 704. After the resist 708 is removed, a second thin oxide film 705 is formed in the trench 704 by thermal oxidation.
Further, as shown in FIG. 5(c), an insulating film 706, which is to be a buried insulating film, is formed on the resulting semiconductor substrate 701. Here, the surface 706a of the insulating film 706 on and around the etching-stop layer 703 is higher than the surface of the insulating film 706 in other regions.
Then, as shown in FIG. 5(d), the surface of the insulating film 706 is polished by a CMP method until the surface 703a of the etching-stop layer is exposed. Thereby, a device isolation region can be formed of the buried insulating film 707 whose surface is flat.
However, degree of flatness of the buried insulating film obtained by the above-described method depends greatly on a pattern in which device isolation regions, active regions and the like are configured.
More particularly, where the trench has a large width (i.e., the device isolation region is wide), the insulating film 704, especially in a central portion M of the trench 704, is polished into a thin film, as shown in FIG. 6. That is, there arises a problem of a so-called dishing phenomenon. As a result, the insulating film 706 becomes thinner where the device isolation region has a large width, while the insulating film 706 is thicker where the device isolation region has a small width. That leads to unevenness of the surface of the insulating film 706 and makes it difficult to perform a pattern for interconnections or the like to be formed thereon later. Besides, the thinned insulating film 706 brings about the problem that capacity increases between the substrate and interconnections, which results in a delay in operation of circuitry.
Also as illustrated in FIG. 6, when the insulating film 706 is polished so that an area where active regions are densely formed is flattened, the etching-stop layer 703 is completely polished away and the surface of the semiconductor substrate 701 is also polished where active regions are isolated and narrow. As a result, there arises a problem in that electric properties of devices formed thereon deteriorate.
Furthermore, as shown in FIG. 7, in the case where an active region of different width co-exists, the insulating film 706 is not completely polished away by the CMP method in an area including a wide active region, while in an area including a narrow active region, not only the insulating film 706 but the etching-stop layer 703 is completely removed even in the middle of the polishing process.
To cope with this problem, Japanese Unexamined Patent Publication No. HEI 8(1996)-46032 proposes a method for flattening the surface of device isolation regions by relatively simple steps.
According to this method, as shown in FIG. 8(a), a pad oxide film 102 and an etching-stop layer 103 of polysilicon are deposited on a P-type semiconductor substrate 101, first. Then, the etching-stop layer 103,the pad oxide film 102 and the semiconductor substrate 101 in a device isolation region-to-be are sequentially etched using a resist (not shown) as a mask to form a trench 104 in the semiconductor substrate 101. Thus a mesa portion is formed on the semiconductor substrate 101. Then, the resist is removed.
Subsequently, as shown in FIG. 8(b), a second thin oxide film 105 is formed on the entire surface of the resulting semiconductor substrate 101 by thermal oxidation. A buried insulating film 106 is formed by a bias ECR (electron-cyclotron resonance) method, and an etching-stop layer 107 of polysilicon is further deposited.
Then, as shown in FIG. 8(c), a convex portion of the etching-stop layer 107 is flattened by a silicon polishing technique to expose the surface of a convex portion of the buried insulating film 106.
As shown in FIG. 8(d), the buried insulating film 106 is etched by an RIE (reactive ion etching) method using the etching-stop layer 107 as a mask to expose the etching-stop layer 103.
Further, as shown in FIG. 8(e), an exposed portion of the etching-stop layer 103 as well as the etching-stop layer 107 are removed.
By the above-described steps, a protruding portion 109 of the buried insulating film 106 and a remaining portion 110 of the etching-stop layer 103 are formed on the mesa portion of the semiconductor substrate 101.
Then, as shown in FIG. 8(f), the surface of the resulting semiconductor substrate 101 is polished to be flattened. It is noted that, in the polishing process, a portion having a small area can be readily polished because the small-area portion receives a higher polishing pressure. Therefore, the protruding portion 109 of the buried insulating film 106 and the remaining portion 110 of the etching-stop layer 103 can be easily removed regardless of irregularities on the surface of the semiconductor substrate 101.
In this method, however, when the convex portion of the etching-stop layer 107 is flattened to expose the convex portion of the buried insulating film 106 as shown in FIG. 8(c), the dishing phenomenon takes place and the buried insulating film 106 in the trench 104 is exposed if the trench 104 has a large width (the device isolation region is wide) as shown in FIG. 9(a).
As a result, as shown in FIG. 9(b), the exposed portion of the buried insulating film 106 is etched at the later etching step by the RIE method. As a result, this portion of the buried insulating film 106 is removed in the form of a trench, and step difference is produced in the buried insulating film 106, which further makes difficult the patterning in a later step.
The present invention provides a process for fabricating a semiconductor device comprising the steps of: forming an etching-stop layer on a semiconductor substrate; patterning the etching-stop layer so that the etching-stop layer remains in a region to be an active region and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the semiconductor substrate an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer above the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting semiconductor substrate for flattening after removing the resist pattern.
In another aspect, the present invention provides a process for fabricating a semiconductor device comprising the steps of: forming an etching-stop layer on a wafer providing a plurality of semiconductor substrates; patterning the etching-stop layer using a resist as a mask so that the etching-stop layer remains in a region to be an active region and in a peripheral region of the wafer and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the wafer an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer in the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value and in the peripheral region of the wafer, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting wafer for flattening after removing the resist pattern.
In other words, in view of the above-described problems, an object of the present invention is to provide a process for fabricating a semiconductor device which enables reproducible formation of a device isolation region from a buried insulating film having a flatter surface regardless of the width of the device isolation region and an active region.